[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #129 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/qemu/qemu/blob/master/target/ppc/translate.c#L950

eurrrgh... macros-on-macros-on-macros... *sigh*.

ok so we're looking at a trail that goes through GEN_HANDLER, GEN_OPCODE,
GEN_INT_ARITH_ADD but ultimately lands at geo_op_addic which in turn
lands in gen_op_arith_add.

here's where addco sets the flags compute_ca=1, compute_ov=1 *but* sets
add_ca=0 whereas addeo *does* set all three (line #926)

https://github.com/qemu/qemu/blob/master/target/ppc/translate.c#L924

the flag "cpu_ca" comes in globally (initialised at line 132).

looking at the spec, the difference between addco and addeo is supposed to
be:

addco

RT <= (RA) + (RB)
The sum (RA) + (RB) is placed into register RT.

addeo

RT <= (RA) + (RB) + CA
The sum (RA) + (RB) + CA is placed into register RT.

hmmm need to look at microwatt, will do that in a minute.

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