[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Thu Mar 26 16:52:54 GMT 2020


--- Comment #122 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Michael Nolan from comment #121)

> > that _should_ be sufficient to get sub, subi and neg all working, with not a
> > lot of effort.
> Working now.

yay!  oh wait...

FAIL: test_sub (__main__.DecoderTestCase)
Traceback (most recent call last):
  File "simulator/test_sim.py", line 98, in test_sub
    self.run_test_program(program, [1, 2, 3, 4, 5])
  File "simulator/test_sim.py", line 105, in run_test_program
    qemu_register_compare(simulator, q, reglist)
  File "simulator/test_sim.py", line 111, in qemu_register_compare
    simulator.regfile.assert_gpr(reg, qemu_val)
  File "/home/lkcl/src/libreriscv/soc/src/soc/simulator/internalop_sim.py",
line 74, in assert_gpr
    assert reg_val == val, msg
AssertionError: reg r3 got 10000000000004444, expecting 4444

Ran 5 tests in 15.696s

FAILED (failures=1)

how many bits is that
0x 1 0000 0000 0000 4444

ha, that's amusing.  the result is a roll-over from 64-bit arithmetic

> Need to sort out setting the carry and overflow flags at some
> point though, that'll be more fun...

yehyeh.  a SPR storing the carry, first.  take a look at pearpc,
it should show a way to do it (that's easy to interpret)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list