[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #121 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #120)

> 
> should be very straightforward (you want to do it?) a separate if elif elif,
> "if op1.value == Op1.ONE op1 += 1"
> 
> can skip carry for now, add as TODO.
> 
> then also if row['op1neg'] op1 ^= 0xffffffffffffffff
> 
> something like that.
> 
> or op1 = (~op1) & 0xffffffffffffffff
> 
> that _should_ be sufficient to get sub, subi and neg all working, with not a
> lot of effort.

Working now. Need to sort out setting the carry and overflow flags at some
point though, that'll be more fun...

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