[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[Luke Kenneth Casson Leighton]

On Wednesday, March 25, 2020, <bugzilla-daemon at libre-riscv.org> wrote:

> http://bugs.libre-riscv.org/show_bug.cgi?id=186
>
> --- Comment #110 from Michael Nolan <mtnolan2640 at gmail.com> ---
> I've got a rudimentary qemu-gdb interface working in qemu.py:
> https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/
> simulator/qemu.py;h=70e29b0d76b65227a06d3ba3bd95315cf5af37e8;hb=
> 3f7e6c771c7f8df65e67e6dc350964a54aee8066
>
> It's able to load a kernel into qemu, set up a breakpoint at the start of
> it,
> single step it, and dump the register contents.


coooool.

confirmed able to duplicate that, here.

i did encounter KeyError, register-values not present but it is spurious
and unreliably occurring.

i added an assert to investigate and, sigh, was no longer seeing failures
even after running 20 times.

the other really useful addition would be memory-dump / memory location
reading.

btw change of topic, i noticed, just like in the original RegSim, OP_ADD is
not joined by OP_SUB because Anton chose to do "add1 to op1" as well as
"invert op1" in the InternalOp csv.

therefore we need to pass the whole of the decode row to the
execute_alu_sim function, rather than just the enum InternalOp value.




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