[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #110 from Michael Nolan <mtnolan2640 at gmail.com> ---
I've got a rudimentary qemu-gdb interface working in qemu.py:
https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/qemu.py;h=70e29b0d76b65227a06d3ba3bd95315cf5af37e8;hb=3f7e6c771c7f8df65e67e6dc350964a54aee8066

It's able to load a kernel into qemu, set up a breakpoint at the start of it,
single step it, and dump the register contents.

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