[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Wed Mar 25 21:20:35 GMT 2020


--- Comment #110 from Michael Nolan <mtnolan2640 at gmail.com> ---
I've got a rudimentary qemu-gdb interface working in qemu.py:

It's able to load a kernel into qemu, set up a breakpoint at the start of it,
single step it, and dump the register contents.

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