[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #103 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #102)
> (In reply to Luke Kenneth Casson Leighton from comment #98)
> > https://git.libre-riscv.org/?p=soc.git;a=blob;f=src/soc/simulator/test_sim.
> > py;hb=HEAD
> > 
> > y'know... the comment "checked this against qemu" got me thinking. this
> > looks like it could be used to actually run any of:
> > 
> > * qemu
> 
> what do you think, michael: does firing off qemu to run those same
> (tiny) binaries sound practical?

It doesn't seem like a bad idea, especially since we don't have another power
simulator to compare to yet. Getting the instructions/data into qemu is pretty
easy, just compile and link a bare metal kernel. I've got a folder with my
manual method for this already, and I can add it to the git repo. 
However, getting the data (registers/memory) out of qemu might be a bit harder.
Probably the best way would be to use the gdb socket that qemu makes available
for reading registers and memory. I know GDB is written with python in mind, so
it *should* be doable to control it from python, but I haven't investigated
that yet.

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