[libre-riscv-dev] Advanced Topics on RISCV

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Tue Mar 24 12:58:29 GMT 2020

> given that AMOs are not very common, they basically get away with this
> approach.  however for massively-parallel SMP systems (64 cores or
> greater) this approach would begin to result in significant contention
> and slow-down of certain tasks.

So how would you get around this for >64 core RISCV CPU?


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