[libre-riscv-dev] Advanced Topics on RISCV

[Jean-Paul Chaput]

Hello Immanuel,

About manycores, we did a lot of work on that topic in our lab
(Sorbonne Université/LIP6). I send you a reference toward the
project we developed. This is a huge lot of work and may take
a lot of time to understand. But, we made a real chip with
16 cores to prove it works (and it do work). I cannot give you
more technical information as it not my field of expertise.

You must distinguish two case:

* Multi cores ( < 16) in that case, simpler solutions can be
  used.

* Many cores ( > 16) in this case, the TSAR project can be
  of interest.

TSAR (Tera-Scale ARchitecture).

You can see details here:
    https://www-soc.lip6.fr/trac/tsar

Best regards,


PS: Already signaled it to Luke.


On Tue, 2020-03-24 at 11:51 +0000, Immanuel, Yehowshua U wrote:
> I’ve read through the Spike page and a good portion of the simpleV page.
> 
> My two goals at the moment are:
> 1. Understand how RISCV handles multiple processes and does page walking
> 2. Understand how multicore ROSCV would work
> 
> I’m hoping to play with FreeRTOS soon so I can run through its codebase for setting up
> page tables.
> Also, do you know if spike tests the special instructions like exception instructions?
> Also, what RISCV instructions would a kernel use to set up the pagetables?
> 
> Lastly, do you know any good resources for intro to multicore systems? RISCV doesn’t
> seem to have any multicore specific instructions. My current questions would include
> things like:
> 
> 1. How can the kernel assign tasks to a certain core? If you have a process with
> multiple threads, it would make sense to spread out the threads among available
> processors instead of concentrating them on a single core. How might this work with
> respect to RISCV?
> 
> 2. Does the hardware ensure cache coherency - that is - externally - software sees one
> big cache all though I imagine each core would have a local cache that would have to
> communicate with other caches?
> 
> Yehowshua
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