[libre-riscv-dev] Status on Our RISCV Implementation

[Luke Kenneth Casson Leighton]

On Tue, Mar 24, 2020 at 11:39 AM Immanuel, Yehowshua U
<yimmanuel3 at gatech.edu> wrote:
>
> I’m curious, what is the status of our RISCV implementation.
>
> Do we have:
> 1. A decoder - I’m pretty sure we do

using minerva: it will need updating to RV64GC

> 2. A page table walker

nope.  not for RISC-V.

> 3. FPU support

yes.

> 4. Supervisor/Hypervisor mode support?

nope.  not for RISC-V.  userspace only.

l.