[libre-riscv-dev] Advanced Topics on RISCV

Immanuel, Yehowshua U yimmanuel3 at gatech.edu
Tue Mar 24 11:51:56 GMT 2020

I’ve read through the Spike page and a good portion of the simpleV page.

My two goals at the moment are:
1. Understand how RISCV handles multiple processes and does page walking
2. Understand how multicore ROSCV would work

I’m hoping to play with FreeRTOS soon so I can run through its codebase for setting up page tables.
Also, do you know if spike tests the special instructions like exception instructions? Also, what RISCV instructions would a kernel use to set up the pagetables?

Lastly, do you know any good resources for intro to multicore systems? RISCV doesn’t seem to have any multicore specific instructions. My current questions would include things like:

1. How can the kernel assign tasks to a certain core? If you have a process with multiple threads, it would make sense to spread out the threads among available processors instead of concentrating them on a single core. How might this work with respect to RISCV?

2. Does the hardware ensure cache coherency - that is - externally - software sees one big cache all though I imagine each core would have a local cache that would have to communicate with other caches?


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