[libre-riscv-dev] [Bug 264] ISA switch needs to be a privileged operation

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Mar 23 01:12:01 GMT 2020


--- Comment #3 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #2)
> (In reply to Jacob Lifshay from comment #1)
> > it's perfectly fine to not support particular pairs (such as if the second
> > one can trap and the first one can't just be run again -- allowing us to not
> > need to worry about what happens if we trap in the middle of a pair).
> hmm... we might have to. or, another way (indicating the extent of the
> awfulness), a bit in a SPR which is contextswitched tells us which of the 2
> C instructions are being executed.

That could work, but it will require additional modification to Linux as well
as userspace for things like changing the on-stack structures for asynchronous

> or... *shudder* we have the PC advance first by 4 bytes, then jump BACK 2
> bytes, then jump forward to...

That would be very messy and won't work if any instructions don't start on a
4-byte boundary (can happen with 48-bit instructions), since that would be
ambiguous between a misaligned 4-byte instruction and the second half of a
compressed instruction pair.

> ... no, my brain just melted thinking about that
> one.

Let's all join the melted brain club!!! :P

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