[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #6 from Jacob Lifshay <programmerjake at gmail.com> ---
Was assuming that the L1 cache has a single cache-line-sized R or W port,
though having 2 ports makes it even better.

Remember that we probably want another cache-line-sized port for communication
with the L2 and the rest of the SoC.

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