[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=257

--- Comment #5 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #4)
> ok, reopening

thanks.  whew.  oh.  one other thing: if it can be N-way-ported (assume that
the L1 cache will at some point be dual-ported, minimum) that would be handy. 
if there are several LDs, on 16-byte boundaries for example, we don't want the
L1 cache to be the bottleneck just because it's only possible to read/write one
cache line at a time.

i'm keeeenly aware that this implies we would be need a maaassive 256-bit-wide
data bus to the L1 cache.

oink.

welcome to GPUs :)

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