[libre-riscv-dev] [Bug 258] Finish implementing support for Power in simple-soft-float

[Jacob Lifshay]

On Tue, Mar 17, 2020, 23:58 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> On Wednesday, March 18, 2020, <bugzilla-daemon at libre-riscv.org> wrote:
>
> > http://bugs.libre-riscv.org/show_bug.cgi?id=258
> >
> > --- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
> > Just finished some refactoring in preparation for supporting Power's
> weird
> > FP
> > status flags.
>
>
>  the FP HDL needs a big update to bring out status bits.  then another one
> to add rounding modes, which is quite a bit of work.
>

Adding status bits and adding rounding modes should be done together,
because they are closely interrelated, especially inexact and underflow.

If you do them separately, you will only be making more work for yourself.

Jacob