[libre-riscv-dev] [Bug 258] Finish implementing support for Power in simple-soft-float

Luke Kenneth Casson Leighton lkcl at lkcl.net
Wed Mar 18 06:57:42 GMT 2020

On Wednesday, March 18, 2020, <bugzilla-daemon at libre-riscv.org> wrote:

> http://bugs.libre-riscv.org/show_bug.cgi?id=258
> --- Comment #1 from Jacob Lifshay <programmerjake at gmail.com> ---
> Just finished some refactoring in preparation for supporting Power's weird
> FP
> status flags.

 the FP HDL needs a big update to bring out status bits.  then another one
to add rounding modes, which is quite a bit of work.


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