[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Tue Mar 17 13:48:05 GMT 2020


--- Comment #22 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jock Tanner from comment #21)
> (In reply to Luke Kenneth Casson Leighton from comment #20)
> > ok try that, jock - but before doing so, have a look at alu16.ap
> > (if you can)
> I dug up this:
> http://manpages.ubuntu.com/manpages/bionic/man5/ap.5.html
> and I looked at the file knowing approximately what kind of problem it
> solves. 

sorry, sorry, i meant "look at it with make cgt" followed by "File-Open"
and type "alu16".

or, yes, use "cgt --script=doAlu16"

the .ap files are basically purely positions of components etc. and the
tracks.  looking at them (directly) will drive you nuts :)

> I pulled your changes and did only
>   make clean
>   make lvx
>   cgt --script=doAlu16
> Still I got exactly the same error as before. 

arse.  oh wait - don't run "make lvx".  i just tried that, and yes i got
an error.

do this:

make clean
make vst               <---- makes the VHDL
cgt --script=doAlu16

the reason is: "make lvx" will *already create* the .ap files.  however - and
this is quite smart - doAlu16.py is instructed to *pick up* (read) them if they
exist, because we might want to do a bit of work (some place), then save them,
and do some routing later on.

loadCell Catalog.State.Logical will load only the VHDL files (alu16.vhd
then add.vhd and sub.vhd because those are sub-components)

loadCell Catalog.State.Views will load *everything* that exists:
alu16.vhd, alu16.ap, *and* the sub-components of those as well
(add.vhd, add.ap, sub.vhd, sub.ap - you can see the hierarchy
in the log output)

> And the picture is just a
> quarter of the 'make view' picture size.

that's ok - just resize it then press "F"

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