[libre-riscv-dev] [Bug 206] Implement branch prediction

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=206

--- Comment #20 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #19)
> that means the SRAM has to be dual-ported, and if we do dual-issue it'll be
> *quad* ported.
> 
> eek

I didn't look, but all we need to do is steal one of the ports while correcting
mispredictions -- those are rare enough that slowing down fetch while fixing up
the tables is acceptable.

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