[libre-riscv-dev] go die/cancel signals in fsm

[Luke Kenneth Casson Leighton]

On Wed, Jul 22, 2020 at 10:51 AM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> > This is
> > needed to not have to wait 63(!) more clock cycles for a canceled div
> > instruction to finish computing before another div instruction can be
> > started.
>
> indeed.

for now, you can see that issuer.py is a FSM:
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;hb=HEAD#l124

so there's not going to be any cancellation.  instructions are done
one at a time, total freeze until the instruction is completed.

l.