[libre-riscv-dev] go die/cancel signals in fsm

[Jacob Lifshay]

I looked through the vcd generated for soc.simple.test.test_core and
was unable to locate the signals used to tell the pipeline stages that
the instruction they are currently operating on is canceled. This is
needed to not have to wait 63(!) more clock cycles for a canceled div
instruction to finish computing before another div instruction can be
started.

Help wanted,
Jacob