[libre-riscv-dev] daily kan-ban update 19jul2020

[Luke Kenneth Casson Leighton]

On Sunday, July 19, 2020, Yehowshua <yimmanuel3 at gatech.edu> wrote:

> >
> > in our case that's 17,000 flattened signals.
>
> Verilator retains the hierarchy of whatever it consumes.
> SO you’ll get a hierarchical CPU and flat peripherals.


thank goodness for that.

many of the pipeline signals have not been given globally unique names,
meaning there's dozens of duplicate "ready_o" etc. and more.

l.



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