[libre-riscv-dev] litex and libre-soc

[Luke Kenneth Casson Leighton]

On Wed, Jul 8, 2020 at 12:24 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
> Regarding our discussion about litex and libre-soc have you tried to contact LambdaConcept ?

over 18 months ago, yes.  the context at the time was that we were
expecting to do an augmentation of RISC-V, and consequently, starting
from Minerva would have saved us a hell of a lot of time.

> You already seem to sometimes use Minerva core as reference.

it's more than that: the Load/Store and Fetch Interfaces are perfectly
well-suited generic pieces of code, so aside from expanding to 64 bit
data and 48 bit addressing, can be used pretty much as-is.


> He also seems
> to be familiar with porting litex things to nmigen (https://github.com/jeanthom/gram)
> and is based in Europe.

yes.  jean thomas was on the MarketNext call.  unfortunately it was
billed as a "single day" event, and the productivity (return) for that
would be very low.  he was expecting it to be short, where what we
need is much more mid- to longer-term help.

On Wed, Jul 8, 2020 at 1:48 PM Yehowshua <yimmanuel3 at gatech.edu> wrote:
>
> I’ve been keeping tabs on Lambda concept.
> They are currently working on bringing a DRAM
> controller to nmigen.

if enough people commit to nmigen peripherals we may actually be able
to use it fully, instead of litex, where code basically has to be
compiled to verilog and run under verilator, as it's the "common
denominator" to both migen and nmigen.

a DRAM controller for nmigen would be a significant step in that direction.

l.