[libre-riscv-dev] 130nm for the hackers : finally a reality ?

[Luke Kenneth Casson Leighton]

found one:

https://gitlab.raptorengineering.com/tpearson/litex-boards/-/blob/wishbone_8bit_malfunction/litex_boards/targets/rtl/test_wb_module.v
https://gitlab.raptorengineering.com/tpearson/litex-boards/-/blob/wishbone_8bit_malfunction/litex_boards/targets/versa_ecp5.py

see TestModule.

basically, what both you - and i - want to do is to stick to nmigen
and to define peripherals and the full chip interconnect in nmigen,
where i would like (in addition to that) the IO and peripherals to be
specifiable in some machine-readable text form.

unfortunately, litex does a lot more than just the HDL.

l.