[libre-riscv-dev] daily kan-ban update 05jul2020
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Sun Jul 5 12:33:47 BST 2020
* started the spr pipeline
* started a test_trap_compunit.py (doesn't work yet)
* renamed some spr pipe_data.py to fast to avoid confusion with slow spr regfile
* better trap register checking (particularly SPRs)
* sorted out SPR naming in ISAcaller simulator
* made it possible for trap to be used "microcode" fashion. first
use: illegal instructions.
* talked with Staf about IO pads and how to use litex
* reviewed Staf's JTAG code (thinking how to do debug in hardware)
* reviewed microwatt core_debug.vhdl
* managed to track down why qemu was blocking when traps occur: a
breakpoint was missing on 0x700.
* made the simulator possible to start from an address other than 0x00000000
* added OP_SC back in
* created an SPR CompUnit (disabled for now)
rest of day: don't, know, there's a lot of little tasks like this need
doing, so it's unpredictable. nothing big to focus on for an entire
these are the tasks. *i need help with them*.
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
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