[libre-riscv-dev] 130nm for the hackers : finally a reality ?
staf at fibraservi.eu
Fri Jul 3 19:13:10 BST 2020
Luke Kenneth Casson Leighton schreef op vr 03-07-2020 om 15:26 [+0100]:
> if you are suggesting to use litex soc.py to simply create a "bare"
> verilog file - with no UART, no SPI, no SDRAM, nothing - no
> "Controllers" at all, then this i do not recommend or advocate.
Indeed, coming from an ASIC background when I talk about IO I mean the
IO pads indeed. The peripherals themselves are 'just' RTL.
> if however you are suggesting to use litex to create a bare verilog
> *including* the peripheral HDL and full wishbone interconnect (but
> stop at the FPGA side) this i believe is very sensible.
Indeed that is what I am suggesting.
> * you *might* be referring to IO as the "actual pads". if that is the
> case then yes, i agree this would also be sensible to not have litex
> try to handle that: to have that done through nmigen.
> the only thing is, that's a *lot* of Signals so i think it would be a
> good idea to have litex output a text, JSON or CSV file containing the
> list of peripherals and their pinouts.
Actually all the signals will be inputs and outputs from the top
verilog. The platform class can also write it to a second file but this
would be redundant information. You will actually define these signals
in a platform file specific to the chip; e.g. starting from a file in
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