[libre-riscv-dev] 130nm for the hackers : finally a reality ?
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Fri Jul 3 15:26:07 BST 2020
On Fri, Jul 3, 2020 at 2:49 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Nono, one would still use soc.py as it is just add a platform that spits out a verilog file of the whole soc top and not call the FPGA tool chain for synthesis and P&R.
> This top verilog would then be used through Instance in nmigen and combined with IO and go through Coriolis flow.
right, yes, got it - am with you now. i think. hang on. the mention
of "IO" part has me needing to double-check.
* litex is not just a soc "caller / FPGA tool helper", it is a
peripheral (IO) and Bus interconnect "creater". nothing as
sophisticated as OpenPITON but still good. need a UART, call
soc.add_uart() function. need an SPI peripheral, call soc.add_spi()
and so on.
* by calling soc.add_uart() etc. litex not only pulls in HDL for that
peripheral it also creates the entire wishbone bus slave, sets it up
at a suitable memory location, sets up the CSRs - everything.
if you are suggesting to use litex soc.py to simply create a "bare"
verilog file - with no UART, no SPI, no SDRAM, nothing - no
"Controllers" at all, then this i do not recommend or advocate.
if however you are suggesting to use litex to create a bare verilog
*including* the peripheral HDL and full wishbone interconnect (but
stop at the FPGA side) this i believe is very sensible.
* you *might* be referring to IO as the "actual pads". if that is the
case then yes, i agree this would also be sensible to not have litex
try to handle that: to have that done through nmigen.
the only thing is, that's a *lot* of Signals so i think it would be a
good idea to have litex output a text, JSON or CSV file containing the
list of peripherals and their pinouts.
(*sigh* this is what the pinmux.py program is supposed to be for)
with litex outputting the verilog soc *AND* a machine-readable list of
peripherals with their pins, the nmigen part can pick those up, create
the IO (actual pads) part very easily, without there being
transcription errors that creep in when this is done manually. and,
adding another peripheral is also easy.
what do you think?
More information about the libre-riscv-dev