[libre-riscv-dev] 130nm for the hackers : finally a reality ?

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op wo 01-07-2020 om 13:46 [+0100]:
> ---crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> 
> On Wed, Jul 1, 2020 at 12:56 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> 
> we initially thought there would be time to fit FP pipelines in:that's not going to be possible.  therefore what we'll have time to dowill actually be a lot smaller than that.  which leaves a bit moremoney spare for you, btw.  or, the opportunity to fit extra thingsonto the die (on the same wishbone bus) if you like?

What is time-line that would fit ?
Google announced to do a run somewhere in November but did not specify when the design has to be ready for the tape-out. So this is an unknown.
I did put end of October for design to be finished to have some room to get the design P&Red and DRC clean for the actual tape-out mid November; imec also wants first layout two weeks before that final tape-out date, e.g. therefor the end of October deadline.
So there are 4 months left; maybe some of the formal proof can be done after tape-out etc. ?
> indeed.  well with a smaller ASIC, you get more :)  the availablebudget does not change.

For the external manufactured things we agreed on paying the money based on the invoice from imec, this was also to take into account to possibility that the prototype would take more area.
If we use less budget I suppose part of that budget could be retargeted for the 0.13um run we may do afterwards. But let's have this discussion when it becomes more clear how much area actually will be used by the prototype.

> > For the 0.18um prototype we can go up to 208 pins for a QFP with 0.5mm pin pitch or even 256 pins for a LQFP with 0.4 pin pitch.
> 
> it's likely we'll be below this simply on time it takes to testdifferent peripherals in an FPGA.

I thought you were going to use litex peripherals which I think should already be tested. With some precautions to be sure to not cause the full chip to fail we can put not-fully tested peripherals on the design. Also IO not used by peripherals can be GPIO pins.

greets,
Staf.