[libre-riscv-dev] 130nm for the hackers : finally a reality ?
Luke Kenneth Casson Leighton
lkcl at lkcl.net
Wed Jul 1 13:46:41 BST 2020
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
On Wed, Jul 1, 2020 at 12:56 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> Luke Kenneth Casson Leighton schreef op wo 01-07-2020 om 12:02 [+0100]:
> > ok. 180nm is 70,000 gates per sq.mm, therefore (square law), 130nm is
> > double that. (180/130 * 180/130). so that's 1.4 million gates.
> You have also count the area of the on-chip ram. Also be aware that ASIC gates is different from FPGA gates. ASIC gates are based on NAND2 standard cell, FPGA gates on LUTs. In my previous live I've seen quite some debate on how to convert them. I think 1 FPGA gate corresponds with 6-12 ASIC gates depending on architecture.
ironically i am used to thinking in ASIC terms not FPGA terms.
> Cost for the 0.18um prototype was based on 36mm2 so in 0.13um this would correspond with 18mm2 so won't fit on the Sky130 runs.
we initially thought there would be time to fit FP pipelines in:
that's not going to be possible. therefore what we'll have time to do
will actually be a lot smaller than that. which leaves a bit more
money spare for you, btw. or, the opportunity to fit extra things
onto the die (on the same wishbone bus) if you like?
> > we'd really need to speak with Staf, as it means moving from October180nm with Eurocircuits, to November 130nm.
> I would like to propose to not change the current NLNet defined projects for me and LIP6 in the mids of them.
this makes sense. ok, we stick with what we agreed, and we adjust accordingly.
> I did spend quite some time on defining them and trying to guide them in order to be able to reach a successful tape-out. I did count on being able to finalize the milestones in the NLNet project and be paid for my work.
indeed. well with a smaller ASIC, you get more :) the available
budget does not change.
> The package will also be BGA which is a pain to solder oneself.
yes. been there.
> For the 0.18um prototype we can go up to 208 pins for a QFP with 0.5mm pin pitch or even 256 pins for a LQFP with 0.4 pin pitch.
it's likely we'll be below this simply on time it takes to test
different peripherals in an FPGA.
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