[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #38 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
https://github.com/lambdaconcept/minerva/blob/master/minerva/units/decoder.py#L140

found it :)

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