[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #143 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ok so whatever was going on in doAlu16.py, where the tracks were not
being created (but VIAs were), i cut/paste RingOscillator.py, then
dropped add.ap creation *into* that base, rather than try it the other
way round, and it's worked.

so i now have a VDD / VSS "ring" around add.ap

in the previous experiment, where add.ap and sub.ap was dropped into alu_hier
Cell, the auto-router would connect up a[0..15], b[0..15] and o[0..15] into
the *MIDDLE* of add.ap and sub.ap.

how can that be prevented?  how do you say, "i want the autorouter ONLY
to connect to the input areas defined at the edge"?

(just like a Standard Cell in other words.  really, this is a lot easier
to do by creating a non-standard Cell Library, putting add.ap and sub.ap
into it)

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