[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #133 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #129)
> (In reply to Staf Verhaegen from comment #127)
> 
> > But the use case I am focusing on is people that develop their design using
> > HDL like nmigen or SpinalHDL on a FPGA and then order an ASIC for that. For
> > them the ASIC compilation should be a fully automated process and they
> > should not have to take care of floorplanning.
> 
> if the entire chip in such designs is even as high as 100,000 gates, like
> jeanpaul said, it would take a long time but would still be fine.

In industry target of run length is one night; e.g. new P&R is started before
leaving and results ready the morning next day.
Currently in Coriolis the places and router are single-threaded so there should
be room for improvement there.

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