[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #132 from Staf Verhaegen <staf at fibraservi.eu> ---
(In reply to Luke Kenneth Casson Leighton from comment #131)
> (In reply to Staf Verhaegen from comment #130)
> > Using an analytic placer will naturally get both the input and outputs close
> > the register file and move the middle of the path further away minimizing
> > extra delay from the interconnects.
> 
> that would be really nice to have.  because of the circular nature of the
> design, we may just have to see how it goes.

The Coriolis placer is an analytic placer...
and option 2 of what Jean-Paul proposed is actually doing what I describe...
:)

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