[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon at libre-riscv.org
bugzilla-daemon at libre-riscv.org
Tue Feb 25 11:37:50 GMT 2020
http://bugs.libre-riscv.org/show_bug.cgi?id=178
--- Comment #110 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #108)
> > git clone ssh://gitolite3@git.libre-riscv.org:922/REPONAME.git
>
> OK, I'm stupid. This was actually written on the homepage.
> Not enough caffeine yet.
doh :)
oh, Staf: if there is time, are you going to include a PLL in the test
ASIC in March? (RingOscillator)
jean-paul while you are looking at the ioring ck discrepancies
i am going to investigate the next phase: how to do hierarchical
auto-placement.
i don't believe we need to go the full manual placement route,
just to define (like an ioring) where the inputs/outputs are,
the outer box size, and then auto-place/route from there.
it looks like snx/phenitec06/doSnxCore.py *might* be exactly what
i am looking for (except it doesn't compile at the moment)
- Clock Signal ..........................................
.*ck.*|.*nck.*
- Blockages ...........................................
blockage[Nn]et.*
o Special Cells.
- Pads ..........................................................
.*_px$
[ERROR] Unable to load cell "snx_chip" (option "--cell=...")
o Cleaning up any previous run.
[ERROR] ClockTree: No cell loaded yet.
Python stack trace:
#0 in __init__() at
.../install/lib/python2.7/dist-packages/crlcore/helpers/io.py:166
#1 in ScriptMain() at
.../dist-packages/cumulus/plugins/ClockTreePlugin.py:94
#2 in ScriptMain() at
/home/lkcl/alliance-check-toolkit/bin/doChip.py:195
#3 in <module>() at
/home/lkcl/alliance-check-toolkit/bin/doChip.py:328
[WARNING] No Cell loaded in the editor (yet), nothing done.
Katana.get: Argument type mismatch, should be:<ent> not <none>
mk/pr-coriolis.mk:83: recipe for target 'snx_chip_cts_r.ap' failed
make: [snx_chip_cts_r.ap] Error 1 (ignored)
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