[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #95 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #94)

> ... next challenge... :)  (am currently working out how to do an ioring,
> by looking at the various examples.  i decided to try to "duplicate"
> adder - except in nmigen - as much as possible, even to the point of
> keeping the names of the inputs and outputs the same).

... it doesn't stop... :)

in experiments4 there is a series of mismatches between the cts_r
and ext nets



ck of 'b_2' is NOT connected to ck of 'a_3' in netlist 2
through signal mbk_sig35 but to signal mbk_sig62

ck of 'b_3' is NOT connected to ck of 'a_3' in netlist 2
through signal mbk_sig35 but to signal mbk_sig45


however "make view" actually works which is a really nice surprise.

it is near-identical to the adder example, both the Makefile and ioring.py
any clues?

-- 
You are receiving this mail because:
You are on the CC list for the bug.