[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #94 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #93)
> I've just commited a bug fix in Coriolis so the "part_sig_add" example
> should work. 

found the repo via a git announce email: https://gitlab.lip6.fr/jpc/coriolis

ah! :)

> Dont't hesitate to double check the generated vst to
> confirm that the interfaces are OK now.

there's nothing missing, they're lined up in ls_1.vst, it looks good
jean-paul

> And we absolutely need an independant way to check nMigen vs. extracted
> netlist.

yyeah, beyond that, i have a feeling that one of the important tasks here
will be to work out how to do simulations.  we have unit tests: hmm, they're in
python.  i noticed the RingOscillator simulator input is actually in c.  have
to think about that.

thank you!

... next challenge... :)  (am currently working out how to do an ioring,
by looking at the various examples.  i decided to try to "duplicate"
adder - except in nmigen - as much as possible, even to the point of
keeping the names of the inputs and outputs the same).

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