[libre-riscv-dev] [Bug 186] Create decoder for SOC

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 20:51:28 GMT 2020


--- Comment #16 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #14)
> My issue is not that it can't be implemented correctly in HW, but that
> having the instruction switch the address used halfway through makes it much
> harder to use in a compiler due to the inputs being overwritten part way
> through execution.
> It's the difference between load1 and load2 in:

note that switching to load1 will require a CSR to store the address if the
instruction is interrupted in the middle because the address register may have
already been overwritten.

The load1 semantics should apply to all instructions with scalar/subvector
inputs and vector outputs, where all scalar inputs are read before any outputs
are written. vector (VL-length) inputs are still read and written one
subvector/scalar at a time so we won't need giant temporary buffers.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list