[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #5 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #4)
> (In reply to Luke Kenneth Casson Leighton from comment #3)
> > (In reply to Michael Nolan from comment #1)
> 
> > no stalling is required.
> 
> okok that's not quite true :)
> 
> if the internal multi-issue width is say only 4 64-bit wide, then yes,
> the SimpleV VL-hardware-loop engine (which takes over at this point,
> the lmw decode is "done" by that point) will have to issue 4 instructions
> at a time.
> 
> and, if there are not enough LOAD/STORE Function Units "completed" yet,
> then _yes_, the issue engine has to stall.

Huh ok. So there's a SimpleV translator between the decoder and the dependency
matrices/issue queue?

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