[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #4 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Luke Kenneth Casson Leighton from comment #3)
> (In reply to Michael Nolan from comment #1)

> no stalling is required.

okok that's not quite true :)

if the internal multi-issue width is say only 4 64-bit wide, then yes,
the SimpleV VL-hardware-loop engine (which takes over at this point,
the lmw decode is "done" by that point) will have to issue 4 instructions
at a time.

and, if there are not enough LOAD/STORE Function Units "completed" yet,
then _yes_, the issue engine has to stall.

however this is just day-to-day run-of-the-mill as far as the 6600 engine
is concerned.

if there are no Function Units free to accept the current instruction,
then there are simply too many outstanding instructions being executed
for it to be possible to drop more into the Dependency Matrices.

so... *then* you stall.  that's how it worked back in 1966, the only difference
being now that we will have a multi-issue engine and so can accept more
instructions per clock.

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