[libre-riscv-dev] [Bug 186] Create decoder for SOC

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Mon Feb 24 17:39:39 GMT 2020


--- Comment #2 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Michael Nolan from comment #1)
> The POWER ISA includes instructions to load and store multiple registers
> to/from memory (`lmw` and `smw`). 

A similar situation exists with the load and store string instructions which
are currently "Phased Out" (I assume we wouldn't be implementing these, or
emulating them with an OS trap)

You are receiving this mail because:
You are on the CC list for the bug.

More information about the libre-riscv-dev mailing list