[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #2 from Michael Nolan <mtnolan2640 at gmail.com> ---
(In reply to Michael Nolan from comment #1)
> The POWER ISA includes instructions to load and store multiple registers
> to/from memory (`lmw` and `smw`). 
> 

A similar situation exists with the load and store string instructions which
are currently "Phased Out" (I assume we wouldn't be implementing these, or
emulating them with an OS trap)

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