[libre-riscv-dev] [Bug 186] Create decoder for SOC

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=186

--- Comment #1 from Michael Nolan <mtnolan2640 at gmail.com> ---
The POWER ISA includes instructions to load and store multiple registers
to/from memory (`lmw` and `smw`). 

`lmw rt, D(rA)` loads registers rt, r(t+1), r(t+2), ..., r31 from subsequent
addresses starting at rA + signed(D). `smw` behaves similarly but for stores

These instructions, if implemented, would significantly complicate the decoder
by forcing it to either generate $31-n$ load or store ops while stalling
instruction fetch. Alternatively it could generate a single op that after
taking a trip through the pipeline would be modified (i.e. incrementing rt) and
being placed back into the issue queue. I suspect the latter would not play
nicely with the OOO machinery because it wouldn't place a reservation on a
register until it was time to store that register, so subsequent instructions
could modify the registers before they are stored.

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