[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #90 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
ah.

here's a clue, jean-paul:

  component sm1
    port ( clk   : in bit
         ; rst   : in bit
         ; gates : in bit_vector(1 downto 0)
         ; mask_2 : out bit
         ; mask_0 : out bit
         -- Vector <mask> is holed, unvectorized.
         ; vdd   : linkage bit
         ; vss   : linkage bit
         );
  end component;


  subckt_54_sm1 : sm1
  port map ( clk   => clk
           , rst   => rst
           , gates => pmask(2 downto 1)
           , mask  => 
           , vdd   => vdd
           , vss   => vss
           );

and if you look at the blif file:

.model sm1
.inputs clk gates[0] gates[1] rst
.outputs mask[0] mask[1] mask[2]
.names $false
.names $true
1
.names $undef
.subckt inv_x1 i=rst nq=mask$next[1]
.subckt no2_x1 i0=rst i1=gates[0] nq=mask$next[2]
.subckt sff1_x4 ck=clk i=mask$next[1] q=mask[1]
.subckt sff1_x4 ck=clk i=mask$next[2] q=mask[2]
.names $undef bits[1]
1 1
.names mask[1] mask[0]
1 1
.names mask$next[1] mask$next[0]
1 1
.end

err.... that's not "unvectorised".  i checked the .il file

basically there's some definite corruption going on from BLIF to VST.

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