[libre-riscv-dev] DDR PHY

Cole Poirier colepoirier at gmail.com
Mon Feb 24 15:26:49 GMT 2020

> On Feb 24, 2020, at 5:58 AM, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
> no problem.  i use gmail as well.  the top priority is to disable
> "rich text", always *ALWAYS* expand the [stupid] three dots, and get
> [repeatedly] into the habit of reading the entire message.
> l.

Thanks. Will do :)

One follow up question from my lengthy DDR and PHY questions that you’ve answered above. I believe you said SymbolicEDA will produce a libre PHY for EUR 600,00. I still am struggling to comprehend what PHY “is”, I think essentially I’m having trouble correctly identitfying the separate functionality and the differences in design process and requirements for the controller and the PHY. I understand that *making* our own PHY is vastly beyond the scope of this project, but I think it is still important for me to understand the memory system and how it is synthesized in a non-technical sense in order to better understand the totality of ASIC design and synthesis. I’ve done a lot of googling and I’m still having trouble with this concept, can you point me in the right direction or to a resource that might help me understand better?


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