[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #84 from Jean-Paul.Chaput at lip6.fr ---
(In reply to Jacob Lifshay from comment #83)
> (In reply to Staf Verhaegen from comment #82)
> > > unfortunately as we will be looking at around maybe 30 mm^2 last time we
> > > calculated it, if you remember? if we have appx 25000 gates per mm^2 in
> > > 180nm we are at around 500,000 gates.
> > > 
> > > we simply cannot do a design that large with full flattening.
> > > 
> > > hence the multi stage approach.
> > 
> > Why not ? It's common approach for P&R. Contrary to functions in software
> > source code you don't gain anything by not flattening modules. You only
> > block possible optimizations.

  Set asides that I don't like the full flatten approach, the placer
  and P&R of Coriolis have never been tested with so big designs
  (because there wasn't any until very recenlty). So, to play it
  safe, it is best if there is at least a "plan B" with a design
  broken down in sub-units.

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