[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #83 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Staf Verhaegen from comment #82)
> > unfortunately as we will be looking at around maybe 30 mm^2 last time we
> > calculated it, if you remember? if we have appx 25000 gates per mm^2 in
> > 180nm we are at around 500,000 gates.
> > 
> > we simply cannot do a design that large with full flattening.
> > 
> > hence the multi stage approach.
> 
> Why not ? It's common approach for P&R. Contrary to functions in software
> source code you don't gain anything by not flattening modules. You only
> block possible optimizations.

+1

> 
> And if you really want to keep it hierarchical then I think the right
> approach is to add a special step inside that selectively duplicates modules
> with constant parameters. This will indeed involve C++ programming but why
> do want to exclude that option for this reason ?

Similar to interprocedural constant propagation and function replication in
LLVM.

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