[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #77 from Jean-Paul.Chaput at lip6.fr ---
I'm still investigating the problem of different results between your
version and mine. I made progress and indeed the problem is clearly
around constants generation.

I can reproduce your result if it take the blif file generated by your
version of Yosys. I did locate where the problem comes from analysing
the lvx message (which I agree, is very obfuscated). By looking to
the generated vst file I do see abnormal connections like normal
I/O directly connected to vdd (this should *never* happen with
Alliance/Coriolis). You can see that at 803 of ls_1.vst (instance
subckt_53_sm0).

This results from what is written in part_sig_add.blif starting line
2832. If I understand blif format correctly, this is the truth table
for gates[0], considered as a *logic signal* inside the "ls_1" model
(telling that in fact, gates[0] <= pmask[0]). But this is wrong,
because gates[0] is *not* a *signal* but the *connector* of the
"sm0" subckt (aka, instance). So I humbly suspect that Yosys did
write something wrong. Then the blif2vst tries to make sense of it
and generate strange thing, there I should have a better error
detection and stop with an error.

I'm now in the process of checking with various versions of Yosys
to see if it's a corrected bug or one that did just appears.

It is a good illustration about everyone having exactly the same
versions of the tools to get reproductible results and errors so
we can converge faster.

-- 
You are receiving this mail because:
You are on the CC list for the bug.