[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

bugzilla-daemon at libre-riscv.org bugzilla-daemon at libre-riscv.org
Sun Feb 23 17:55:11 GMT 2020


--- Comment #76 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Staf Verhaegen from comment #75)
> I think the problem is that nmigen assumes you will flatten and optimize the
> design in yosys. This optimization after flattening should normally take
> care of constant propagation.

ah yes that makes sense, it explains a lot, particularly that on flatten it
worked great.

unfortunately as we will be looking at around maybe 30 mm^2 last time we
calculated it, if you remember? if we have appx 25000 gates per mm^2 in 180nm
we are at around 500,000 gates.

we simply cannot do a design that large with full flattening.

hence the multi stage approach.

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