[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #58 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #57)
> The warning about signal connected to POWER/GROUND are just warnings.
> The Blif loader connect them to special cells "zero_x0" or "one_x0".
> 
> I don't know what is the further problem with lvx as I cannot reproduce
> it on my end.

this is make -f Makefile2 lvx... ah sorry, that's part_sig_add.py that
needs to be turned into .il:

soclayout$ python3 examples/part_sig_add.py
soclayout$ make -f Makefile2 lvx

-- 
You are receiving this mail because:
You are on the CC list for the bug.