[libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page

[bugzilla-daemon at libre-riscv.org]

http://bugs.libre-riscv.org/show_bug.cgi?id=178

--- Comment #53 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jean-Paul.Chaput from comment #51)
> I now did make work test_part_add (Makefile3).

confirmed here, w00t! :)

> I almost got part_sig_add to work (Makefile2), but lvx fails due to the
> fact that some external terminals of the netlist are, in fact, unconnecteds.
> That is, in the netlist, you have "carry_in(4)" which is not connected to
> any cell.

okaaay, that will be missing somewhere, one of the adders... ah i think
i know which one, it's the one to do with neg_output.

yes, that one, the carry_in is supposed to be wired to "zeros".
more later, my family has arranged a party :)

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