[libre-riscv-dev] next tasks

[Luke Kenneth Casson Leighton]

On Thursday, February 20, 2020, Staf Verhaegen <staf at fibraservi.eu> wrote:

> Luke Kenneth Casson Leighton schreef op wo 19-02-2020 om 20:25 [+0000]:
>
> > > No, but I do reserve the right to then tape-out a prototype chip
> withsomething else on it.
> >
> > more than happy with that, staf:
>
> But I still assume for now it will be the libre-SOC prototype that will be
> taped and the rest is just an emergency back-up plan.
> It does worry me though that there does not seem a full list of tasks
> still to be performed for this prototype tape-out deadline can happen and
> thus also not the right focus in the development work.


this is because we haven't done anything like this before and consequently
are learning very fast, for the first tine.

i just managed tonight to get a simple ALU in nmigen through coriolis2.


>
> >  i did want to ask you if you wantedto include a basic core anyway on
> the design (i favour the Motorola68000) because we need some sort of "boot
> and power management core".
>
> If everything goes right I'll tape-out the Retro-uC in July on 0.35um with
> a M68K included.


that is fantastic. is it libre licensed (and done in coriolis2) such that
it could be included?


> I may have a closer look at OpenRISC if need be; but as said above this is
> currently not on the table.
>
> greets,
> Staf.
>
>

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