[libre-riscv-dev] next tasks

[Staf Verhaegen]

Luke Kenneth Casson Leighton schreef op wo 19-02-2020 om 20:25 [+0000]:
> On Wed, Feb 19, 2020 at 8:17 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
> > Immanuel, Yehowshua U schreef op wo 19-02-2020 om 14:24 [+0000]:
> > > Also, do keep in mind that while October is a healthy target, if we miss it,  its not the end of the world.
> > 
> > No, but I do reserve the right to then tape-out a prototype chip withsomething else on it.
> 
> more than happy with that, staf:

But I still assume for now it will be the libre-SOC prototype that will be taped and the rest is just an emergency back-up plan.
It does worry me though that there does not seem a full list of tasks still to be performed for this prototype tape-out deadline can happen and thus also not the right focus in the development work.

>  i did want to ask you if you wantedto include a basic core anyway on the design (i favour the Motorola68000) because we need some sort of "boot and power management core".

If everything goes right I'll tape-out the Retro-uC in July on 0.35um with a M68K included.
I may have a closer look at OpenRISC if need be; but as said above this is currently not on the table.

greets,
Staf.