[libre-riscv-dev] Vulkanizing

[Atif Zafar]

I'm thinking completely re-architecting the CPU from scratch with features not seen before such as dataflow/systolic array processing, customizable instructions by the user, customizable data widths etc. It would be a massive effort that would need to be undertaken as a new startup with significant funding and the right team.

Cheers
Atif
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From: Luke Kenneth Casson Leighton <lkcl at lkcl.net>
Sent: Wednesday, February 19, 2020 10:36 AM
To: Atif Zafar <atif at pixilica.com>
Cc: Libre-RISCV General Development <libre-riscv-dev at lists.libre-riscv.org>
Subject: Re: [libre-riscv-dev] Vulkanizing



On Wednesday, February 19, 2020, Atif Zafar <atif at pixilica.com<mailto:atif at pixilica.com>> wrote:
That's awesome Luke. POWER is a great architecture.

it has.. "history".  and IBM and the other members, Freescale, etc, have Serious Clout and prefer to "get things right" if you know what i mean.


Maybe we should consider designing our own CPU with integrated GPU and VPU all from scratch with the best feature set ever designed? There may be interest in that from the people I am working with. Just a thought.

iinterestingg.

were you thinking of basing it *on* another ISA or a completely new set of opcodes, or more along the lines of the underlying hardware?

bear in mind, the idea i came up with (ISAMUX / NS) which is exactly like c++ "using namespace" except at the actual *instruction* level, there's no technical reason why you couldn't literally splice in an entire new GPU-suitable instruction set into a POWER (or RISCV or MIPS) instruction stream

other than the fact that if you do so it means starting from scratch at the compiler level, which is a hell of a lot of additional work, compared to if you leverage *someone else's* preexisting ISA and consequently the preexisting compilers.

so... ISA Level or Hardware level?

l.




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